1. Field of the Invention
The present invention relates generally to a printed circuit board and a method of manufacturing the same and, more particularly, to a capacitor-embedded printed circuit board having one or more blind via holes for providing a high capacitance value in a narrow area of an integrated circuit package or a printed circuit board, and a method of manufacturing the same.
2. Description of the Related Art
With the recent development of semiconductor systems towards high integration and high speed, the operational speed and performance of an entire system, including a semiconductor chip, are determined by external factors as well as the internal factors of the semiconductor chip. Therefore, the most important design factor is to secure signal integrity inside and outside a semiconductor chip.
Furthermore, in electronic systems, the high speed switching of a semiconductor chip and the transmission of a high-frequency signal cause noise attributable to electromagnetic interference. In particular, crosstalk noise and simultaneous switching noise between adjacent lines and input/output pins in high-density circuit designs act as factors to degrade the integrity of signals.
Accordingly, problems, such as ground bouncing and power bouncing, that result from a problem in which a number of semiconductor chips are mounted on a high-density Printed Circuit Board (PCB), thereby consuming large power, must be overcome. As a result, the roles of a decoupling capacitor and a bypass capacitor are very important.
Since conventional passive circuit elements cause resonance in an undesired frequency band due to an inductance value attributable to a lead line, a scheme of inserting passive elements into a PCB to overcome the problem has been proposed in the field of the high-density mounting technology for PCBs.
Until now, discrete chip resistors or discrete chip capacitors have been mounted on the surfaces of most PCBs. However, recently, resistor- or capacitor-embedded PCBs have been developed.
In such embedded PCBs, capacitors are buried outside or inside PCBs. A capacitor that is integrated as part of a PCB is referred to as an “embedded (buried) capacitor,” and a board including such a capacitor is referred to as a “capacitor-embedded PCB” regardless of the size of a PCB.
Conventionally, capacitor-embedded PCB technology may be mainly classified into four methods.
The first one is a polymer thick film type capacitor implementation method that implements a capacitor by applying polymer capacitor paste and thermally setting the paste, that is, drying the paste. This method manufactures an embedded capacitor by printing and drying copper paste to form electrodes after applying polymer capacitor paste to the inner layer of a PCB and drying the paste.
The second one is an embedded discrete type capacitor implementation method that produces a capacitor by coating a PCB with a ceramic filled photo-dielectric resin. In connection with this method, U.S. Motorola Inc. possesses related patent technology. This method implements a discrete capacitor by coating a PCB with a photo-dielectric resin containing ceramic powder, laminating a copper foil to form upper and lower electrodes, forming a circuit pattern and then etching the photo-dielectric resin.
The third one is a method that produces a capacitor by inserting a separate dielectric having capacitance characteristics into the inner layer of a PCB to replace a decoupling capacitor mounted on the surface of the PCB. In connection with the method, U.S. Sanmina SCI Corp. possesses related patent technology. This method implements a power distributed decoupling capacitor by inserting a dielectric composed of a power electrode and a ground electrode into the inner layer of a PCB.
The fourth one relates to a capacitor-embedded PCB in which polymer capacitor paste, which has a high dielectric constant and is composed of a compound of BaTiO3 and epoxy, is charged in a via hole in the inner layer of a PCB, and a method of manufacturing the same. In connection with this method, Korean Samsung Electro-Mechanics Co., Ltd. possesses related patent technology. This method includes eight steps, from the step of forming a plurality of inner layer via holes in a desired portion of a copper foil-layered plate by forming via holes in a PCB to the step of plating the inner walls of outer layer via holes and through holes.
FIGS. 1A through 1N are sectional views illustrating the flow of a prior art method of manufacturing a capacitor-embedded PCB, which relates to the second method described above.
First, a copper-layered plate in which a first copper foil layer 12 is formed on an insulating layer 11 is prepared, as illustrated in FIG. 1A, and then a photo-dielectric material layer 13 is applied on the first copper foil layer 12, as illustrated in FIG. 1B.
Thereafter, a second copper foil layer 14 is layered on the photo-dielectric material layer 13, as illustrated in FIG. 1C, and a photosensitive film 20a is layered on the second copper foil layer, as illustrated in FIG. 1D.
Thereafter, as illustrated in FIG. 1E, a photo-mask 30a on which a desired capacitor pattern is formed is brought into tight contact with the photosensitive film 20a, and ultraviolet rays 40a are radiated onto the photo-mask 30a. At the time, the ultraviolet rays 40a pass through the non-printed portion 31a of the photo-mask 30a, thus forming a set portion 21a in the photosensitive film 20a under the photo-mask 30a, whereas the ultraviolet rays 40a cannot pass through the printed dark portion 32a of the photo-mask 30a, so that a portion 22a in the photosensitive film 20a under the photo-mask 30a remains unset.
Thereafter, as illustrated in FIG. 1F, after the photo-mask 30a has been removed, the unset portion 22a of the photosensitive film 20a is removed by performing a development process such that the set portion 21a of the photosensitive film 20a can remain.
As shown in FIG. 1G, the upper electrode layer 14a of an embedded capacitor is formed in the second copper foil layer 14 by etching the second copper foil layer 14 using the set portion 21a of the photosensitive film 20a as an etching resist.
As shown in FIG. 1H, after the set portion 21a of the photosensitive film 20a has been removed, ultraviolet rays 40b are radiated onto the photo-dielectric material layer 13 while using the upper electrode layer 14a as a mask. At this time, the portion of the photo-dielectric material layer 13 on which the upper electrode layer 14a is not formed absorbs the ultraviolet rays 40b and forms a reacted portion 13b that can be resolved using a special solvent (for example, Gamma-Butyrolactone (GBL)) in a developing process, and the portion of the photo-dielectric material layer 13 on which the upper electrode layer 14a is formed cannot absorb the ultraviolet rays 40b and forms a portion 13a that does not react.
Thereafter, as illustrated in FIG. 1I, the dielectric layer 13a of an embedded capacitor is formed in the photo-dielectric material layer 13 by removing the portion 13b that reacted with the ultraviolet rays 40b through a developing process.
Thereafter, as illustrated in FIG. 1J, the first copper foil layer 12, the dielectric layer 13a and the upper electrode layer 14a are coated with a photosensitive resin 20b. 
Thereafter, as illustrated in FIG. 1K, after a photo-mask 30b in which a desired circuit pattern is formed has been brought into contact with the photosensitive resin 20b, ultraviolet rays 40c are radiated. At this time, ultraviolet rays 40c pass through the non-printed portion 31b of the photo-mask 30b and form a set portion 21b in the photosensitive film 20b under the photo-mask 30b, whereas the ultraviolet rays 40c cannot pass through the printed dark portion 32b of the photo-mask 30b, so that a portion 22b in the photosensitive film 20b under the photo-mask 30b remains unset.
Thereafter, as illustrated in FIG. 1L, after the photo-mask 30b has been removed, the unset portion 22b of the photosensitive film 20b is removed by performing a developing process such that the set portion 21b of the photosensitive film 20b can remain.
Furthermore, as shown in FIG. 1M, the lower electrode layer 12a and circuit pattern 12b of an embedded capacitor are formed in the first copper foil layer 12 by etching the first copper foil layer 12 while using the set portion 21b of the photosensitive resin 20b as an etching resist.
Finally, as shown in FIG. 1N, the set portion 21b of the photosensitive resin 20b is removed. Thereafter, when an insulating layer is layered and a circuit pattern forming process, a solder resist forming process, a nickel/gold plating process and an outline forming process are performed, a capacitor-embedded PCB 10 is manufactured.
U.S. Pat. No. 6,349,456, issued to Motorola, Inc., schematically discloses a method of manufacturing the prior art capacitor-embedded PCB 10 described above.
As described above, the prior art capacitor-embedded PCB 10 is manufactured to exhibit a predetermined capacitance, and the dielectric layer 13a is formed between the two electrode layers 12a and 12b. 
As a result, the capacitance value of the embedded capacitor of the prior art capacitor-embedded PCB 10 is determined by the cross section of the embedded capacitor, the distance between the two electrode layers 12a and 14a and the dielectric constant of the dielectric layer 13a. 
However, since the embedded capacitor used in IC packages or the PCBs based on the prior art method is constructed to have a planar form using a flat copper plate between the layers of a substrate, the prior art embedded capacitor has a structural problem in that a high capacitance value cannot be realized.